Приказ основних података о документу

dc.contributor.authorMitrović, Nikola
dc.contributor.authorDanković, Danijel
dc.contributor.authorRanđelović, Branislav
dc.contributor.authorPrijić, Zoran
dc.contributor.authorStojadinović, Ninoslav
dc.date.accessioned2022-11-04T10:49:15Z
dc.date.available2022-11-04T10:49:15Z
dc.date.issued2020
dc.identifier.citationИИИ 43007 “Истраживање климатских промена и њиховог утицаја на животну средину - праћење утицаја, адаптација и ублажавање”en_US
dc.identifier.citationТР 32012 „Интелигентни Кабинет за Физикалну Медицину – ИКАФИМ“en_US
dc.identifier.urihttps://platon.pr.ac.rs/handle/123456789/882
dc.description.abstractNegative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Change of threshold voltage follow power law tn, where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.en_US
dc.language.isoen_USen_US
dc.publisherМИДЕМ друштво, Словенијаen_US
dc.rightsCC0 1.0 Универзална*
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/*
dc.titleModeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Methoden_US
dc.title.alternativeJournal of Microelectronics, Components and Materials (MIDEM)en_US
dc.typeclanak-u-casopisuen_US
dc.description.versionpublishedVersionen_US
dc.identifier.doihttps://doi.org/10.33180/InfMIDEM2020.305
dc.citation.volume50
dc.citation.issue3
dc.citation.spage205
dc.citation.epage214
dc.subject.keywordsNBTI, VDMOSFET, electrical circuit, modeling, least square methoden_US
dc.type.mCategoryM23en_US
dc.type.mCategoryopenAccessen_US
dc.type.mCategoryM23en_US
dc.type.mCategoryopenAccessen_US
dc.identifier.ISSN0352-9045 (printed)
dc.identifier.ISSN2232-6979 (on-line)


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Приказ основних података о документу

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